Looking for help on this, thank you!

For the processor, assuming all possible forwarding paths, branch decision making in ID stage and hazard detection unit can stall, flush and introduce bubble into the pipeline if necessary. The processor assumes branch not taken and flushes the pipeline if assumption was not correct. Explain your answer by drawing the pipeline diagram. Consider the following instruction sequence that starts at address 0x4000000. 100pY 1d 218 B (v2) OF X4. x7) ] add xy, =i g beg x2; x0. locpn Xor i), sedlia i~z 110 and x13s slidd 5 Consider the processor depicted in the next page. Note that the processor has forwarding unit and hazard detection hardware. For clock cycle 7, first determine the instruction in each stage, then provide values for all signals in the table below (assume the first instruction is Fetched in cycle 1. Provide as much information as you can (e.g., name of the register, content of a memory location, e.g.: R[x1], Mem[x1], R[x1]"R[x2] ). Assume that the original value of R [x1]=0x0abc and R [x2]=0x0100 amiMem[0x0108]=0x0feedbeefandMem[Oanc4]=OxOfeedb4bd IF.Flush Hazard . detection unit D/EX D WB MEM/WB Control M -WB O - + EX/MEM IF ID EX M WB A E 4 - Shift left 2 Registers Instruction 1 Data X =3 PC ALU memory X=3 X-3 memory XCE H C Sign- extend B F Fowarding unit G