Many parallel processing applications require a class of functions implemented as sequences of microfunctions that execute as an unbroken whole (indivisible or atomic operations). This means that when performing these functions foreign microfunctions are not allowed to intervene between microfunctions in the sequence. One way to implement such integral operations is through commands engine of the architecture, so that a single instruction will completely execute such a sequence.

Consider the MDR of the simplified multi-cycle MIPS architecture per command cycle, with both hardwired and microprogrammed logic control, and implement in it for each control case the command: cmpm&addiw $rd,($rs),($rt),($ru),immediateword which, given three memory locations and the immediateword constant, compares the contents of the first memory location with the constant, and in case of equality adds it with the contents of the second position and stores the result of the addition in third memory location, returning in each case the logical result of the comparison. The word-sized constant does not fit inside the instruction, but is placed in the memory location which follows the command.

The operation of the cmpm&addiw command is detailed by the following steps: 1. Reads the memory location referenced by indirect addressing without shifting through the $rs register. 2. Reads the immediateword constant from the memory location following the command. 3. Compares the first value read from memory with the constant. 4. If the two values are equal: Reads the memory location referenced by indirect addressing without shift through the $rt register. Adds the two values read from memory. Stores the result in the memory location referenced by indirect addressing without shifting through the $ru register. 5. Stores in $rd the logical result of the comparison. To implement the cmpm&addiw command, modify the information paths and input options of the MDR subunits accordingly, widening or adding multiplexers where necessary. However, you cannot add submodules or special registers purpose, but you can add write permission to existing registrars. Also, you cannot increase the read ports of the FC. That is why two microfunctions are available to read it, the first reads $rs and $rt, and the second reads the $rs and $ru, selecting the appropriate digit fields from the command word, where the ru field is the 10-6 digit field of the command word. The option to read the FC is done with signal read, which when activated selects the second read, otherwise the first is selected. Assume that the comparison between two values for equality is done in ALM with the cmp microfunction. The logical result of the comparison is stored in C and is also reflected in the Zero digit of the ALM that becomes available at the end of the corresponding microfunction. (Note that Zero=1 means zero ALM output value, so false logic comparison result value.)

For the implementation with hardwired logic control give the sequential states which enable the control signals for the cmpm&addiw command, as well as the conditions transition for all transitions between states. Logical expressions of transition conditions can also contain the digit Zero.

For implementation with microprogrammed logic control, please provide the corresponding microprogram. Corresponding to hardwired logic, microinstructions can contain a conditional jump based on the Zero bit of the ALM. Add new ones if necessary microcommand fields, and define appropriate microfunctions for them. Minimize the instruction cycle time for both implementations of the instruction, without however increase machine cycle time.