Model a 4-bit parallel in left shift register using the above code. Develop a testbench and simulate the design using the stimuli provided below. Assign Clk, Parallelln, load, ShiftEn, Shiftin, RegContent, and ShiftOut. Verify the design in hardware. Name Value 10 ns 50 ng 100 ng 1150 ng 1200 ns 1250 ng 300 ns 0 0 ck_int load_int 1 shift_en_jint shift_in_int aparallel_in_int(3:0) 1 1001 0000 0101 1001 Model a 4-bit parallel in left shift register using the above code. Develop a testbench and simulate the design using the stimuli provided below. Assign Clk, Parallelln, load, ShiftEn, Shiftin, RegContent, and ShiftOut. Verify the design in hardware. Name Value 10 ns 50 ng 100 ng 1150 ng 1200 ns 1250 ng 300 ns 0 0 ck_int load_int 1 shift_en_jint shift_in_int aparallel_in_int(3:0) 1 1001 0000 0101 1001