Question: modify following verilog code as required . . . . Project Description This project involves modeling and implementing a Smart Parking System circuit with the

modify following verilog code as required ....
Project Description
This project involves modeling and implementing a Smart Parking System circuit with the following
features:
Parking Spaces Display:
The system will show the number of available spaces for normal parking (20 spaces) on a
seven-segment display at D1 and D0.
An additional 5 handicapped parking spaces will be displayed on the seven-segment
display at D4.
Entry and Exit Gates:
A real-life parking lot would use separate gates for entry and exit. Here:
Push button M17 will simulate the entry gate for normal parking.
Push button P18 will simulate the exit gate for normal parking.
Push button M18 will simulate the entry gate for handicapped parking.
Push button P17 will simulate the exit gate for handicapped parking.
When any parking section is full (showing 0 spaces available), the respective entry button
will be disabled, and the counter will remain at zero.
Seven-Segment Indicators:
D3 will display "A" when normal parking spaces are available.
D7 and D6 will display "HA" when handicapped parking spaces are available.
Reset Functionality:
A Reset button (N17) will reset the system, restoring:
20 available spaces for normal parking.
5 available spaces for handicapped parking.
LED Indicators:
Green LEDs will be ON when spaces are available:
M16(right green) for normal parking.
R11(left green) for handicapped parking.
Red LEDs will activate when spaces are full:
N15(right red) for normal parking.
N16(left red) for handicapped parking.
Button Debounce:
Debounce circuits will be used for all r_(darr)^("h ") buttons, except for the Reset button.Key Requirements
Simulation:
Accurate simulation is critical to validate the correctness of the code and circuit design. Simulations should be provided for all modules implemented.
Design Specifications:
Use or modify existing modules from previous experiments where applicable.Design additional modules as needed.
Circuit Efficiency:
The design should prioritize efficient use of FPGA resources, such as look-up tables (LUTs), registers, and IOBs.the code:module SmartParkingSystem(
input clk, reset,
input btn_entry_norm, btn_exit_norm,
input btn_entry_hand, btn_exit_hand,
output [3:0] seg_norm, [7:4]seg_hand,
output [7:0] an,
output led_norm_green, led_hand_green,
output led_norm_red, led_hand_red
);
wire debounce_entry_norm, debounce_exit_norm;
wire debounce_entry_hand, debounce_exit_hand;
wire [3:0] norm_spaces, hand_spaces;
wire norm_full, hand_full;
// Debouncing
Debounce db1(clk, btn_entry_norm, debounce_entry_norm);
Debounce db2(clk, btn_exit_norm, debounce_exit_norm);
Debounce db3(clk, btn_entry_hand, debounce_entry_hand);
Debounce db4(clk, btn_exit_hand, debounce_exit_hand);
// Parking Counters
ParkingCounter norm_counter(
clk, reset, debounce_entry_norm, debounce_exit_norm,
4'd20, norm_spaces, norm_full
);
ParkingCounter hand_counter(
clk, reset, debounce_entry_hand, debounce_exit_hand,
4'd5, hand_spaces, hand_full
);
// Seven-Segment Display
SevenSegmentDriver norm_display(norm_spaces, seg_norm);
SevenSegmentDriver hand_display(hand_spaces, seg_hand);
// LED Control
assign led_norm_green = ~norm_full;
assign led_norm_red = norm_full;
assign led_hand_green = ~hand_full;
assign led_hand_red = hand_full;
// Display Control
assign an =8'b11111111; // Modify for multiplexing if required
endmodule;module Debounce(
input clk,
input btn_in,
output reg btn_out
);
reg [19:0] count;
reg btn_state;
always @(posedge clk) begin
if (btn_in != btn_state) begin
count = count +1;
if (count ==20'hFFFFF) begin
btn_state = btn_in;
count =0;
end
end else begin
count =0;
end
end
always @(posedge clk)
btn_out = btn_state;
endmodule;module ParkingCounter(
input clk,
input reset,
input entry,
input exit,
input [3:0] max_spaces,
output reg [3:0] spaces,
output reg full
);
always @(posedge clk or posedge reset) begin
if (reset)
spaces = max_spaces;
else if (entry && spaces >0)
spaces = spaces -1;
else if (exit && spaces max_spaces)
spaces = spaces +1;
end
always @* begin
full =(spaces ==0);
end
endmodule;module SevenSegmentDriver(
input [3:0] digit,
output reg [7:0] seg
);
always @(*) begin
case (digit)
4'd0: seg =8'b11000000;
4'd1: seg =8'b11111001;
4'd2: seg =8'b10100100;
4'd3: seg =8'b10110000;
4'd4: seg =8'b10011001;
4'd5: seg =8'b10010010;
4'd6: seg =8'b10000010;
4'd7: seg =8'b11111000;
4'd8: seg =8'b10000000;
4'd9: seg =8'b10010000;
default: seg =8'b11111111;
endcase
end
endmodule
modify following verilog code as required . . . .

Step by Step Solution

There are 3 Steps involved in it

1 Expert Approved Answer
Step: 1 Unlock blur-text-image
Question Has Been Solved by an Expert!

Get step-by-step solutions from verified subject matter experts

Step: 2 Unlock
Step: 3 Unlock

Students Have Also Explored These Related Programming Questions!