Modify the single cycle datapath to add the support for the following instruction.Instruction: ? ?LWI Rt,Rd(Rs)Interpretation: Reg[Rt] = Mem[Reg[Rd]+Reg[Rs]]Identify Existing blocks used, and suggest new blocks if required. Also suggest if any new control signal is needed.DRAW ON THE DIAGRAM BELOW. YOU CAN DO IT USING ANY SOFTWARE TO DRAW (MSPAINT etc), or you can use your own page and insert a pic below the diagram for answer. Copied solutions will not be accepted and will result in zero marks.

PC A MJX Instruction memory Add Address Instruction Add Data Register # Registers Register # Register # RegWrite Control MJX u ALU operation_ MUX ALU Branch Zero MemWrite Address Data Data memory MemRead