a) How would you extend the single cycle datapath in the figure below to implement the CBNZ (Branch on not zero) Instruction? Similar to CBZ except that the branch is taken when the register is not zero. Explain your work

b) The processor needs to compute the next PC after each instruction. Write a verilog module which computes the next PC. Be sure to include the B, and CBZ cases. You may use the output of the Control module as shown in the figure in the previous problem.

c) How would you extend the single cycle data and control paths in the figure above to implement the BR (Branch to Register) Instruction?

d) Investigate the possibility of adding a new instruction SRBR that combines two existing instructions. For example, SRBR X30, SP, 16 will implement:

ADD SP,SP,16

BR X30 List any additional control or datapaths than need to be added above what is needed for BR. What will be the values of Reg2Loc, UncondBR, Branch, MemToReg, RegWrite, MemRead, MemWrite, ALUSrc, and any control signals you added in the previous problem and added for this problem.

PC Add ALU Add result Shift Reg2Loc Uncondbranch left 2 Branch Mem mRea Instruction B1-21] MemtoReg Control ALU MemWrite ALUSrc RegWrite Instruction 19-5] Read Read Instruction 120-16] 0 register 1 Read address data 1 u Read Zero register 2 nstruction ALU ALU Address Read result data M 131-0 Write register data 2 Instruction nstruction 4-01 memory Write data Registers Write Data data memory 32 Sign 64 Instruction [31-0] ALU extend control Instruction 131-211 PC Add ALU Add result Shift Reg2Loc Uncondbranch left 2 Branch Mem mRea Instruction B1-21] MemtoReg Control ALU MemWrite ALUSrc RegWrite Instruction 19-5] Read Read Instruction 120-16] 0 register 1 Read address data 1 u Read Zero register 2 nstruction ALU ALU Address Read result data M 131-0 Write register data 2 Instruction nstruction 4-01 memory Write data Registers Write Data data memory 32 Sign 64 Instruction [31-0] ALU extend control Instruction 131-211