module maindec$($ Z$\_$flag, opcode, PCSrc$,//$funct$3,///$bne ResultSrc, MemWrite, $//$ALUSrc$,$ ALUSrcA, ALUSrcB, ImmSrc, RegWrite, Jump, ALUop, Branch, Btaken $)$; $//$ input input Z$\_$flag; $//$input $[2$:$0]$funct$3$; $//$bne input $[6$:$0]$ opcode; input Btaken; $//$ output output $[1$:$0]$PCSrc; output reg MemWrite, RegWrite, Jump; output reg $[1$:$0]$ALUSrcA; output reg ALUSrcB; output reg $[1$:$0]$ ResultSrc; output reg $[2$:$0]$ ImmSrc; output reg $[1$:$0]$ ALUop; output reg Branch; assign PCSrc $=($Btaken $==1\text{'}$b$1|$ Jump $==1\text{'}$b$1)?2\text{'}$b$01$ : $2\text{'}$b$00$; $//$assign PCSrc $=($Jump $==1\text{'}$b$1)?2\text{'}$b$10$ : $//($Btaken $==1\text{'}$b$1)?2\text{'}$b$01$ : $2\text{'}$b$00$; always@$(*)$ begin $//$ main decoder case$($opcode$)//\{1,3,2,1,1,2,1,2,1\}7\text{'}$b$000\_0011$ : $\{$RegWrite$,$ ImmSrc, ALUSrcA, ALUSrcB, MemWrite, ResultSrc, Branch, ALUop, Jump$\}=14\text{'}$b$10\_0000\_0000\_0000$; $//$ lw$,$ lbu $7\text{'}$b$010\_0011$ : $\{$RegWrite$,$ ImmSrc, ALUSrcA, ALUSrcB, MemWrite, ResultSrc, Branch, ALUop, Jump$\}=14\text{'}$b$00\_0100\_1100\_0000$; $//$ sw$,$ sb $7\text{'}$b$011\_0011$ : $\{$RegWrite$,$ ImmSrc, ALUSrcA, ALUSrcB, MemWrite, ResultSrc, Branch, ALUop, Jump$\}=14\text{'}$b$1$x$\_$xx$00\_0000\_0100$; $//$ R$-$type, sar $7\text{'}$b$110\_0011$ : $\{$RegWrite$,$ ImmSrc, ALUSrcA, ALUSrcB, MemWrite, ResultSrc, Branch, ALUop, Jump$\}=14\text{'}$b$010\_00$xx$\_1010$; $//$ beq, bne $//7\text{'}$b$110\_0011$ : $\{$RegWrite$,$ ImmSrc, ALUSrc, MemWrite, ResultSrc, Branch, ALUop, Jump$\}=11\text{'}$b$010\_00$xx$\_0010$; $//$ bnes $7\text{'}$b$001\_0011$ : $\{$RegWrite$,$ ImmSrc, ALUSrcA, ALUSrcB, MemWrite, ResultSrc, Branch, ALUop, Jump$\}=14\text{'}$b$100\_1000\_0100$; $//$ I$-$type ALU, slli srli $7\text{'}$b$110\_1111$ : $\{$RegWrite$,$ ImmSrc, ALUSrcA, ALUSrcB, MemWrite, ResultSrc, Branch, ALUop, Jump$\}=14\text{'}$b$111\_$x$010\_0$xx$1$; $//$ jal $7\text{'}$b$011\_0111$ : $\{$RegWrite$,$ ImmSrc, ALUSrcA, ALUSrcB, MemWrite, ResultSrc, Branch, ALUop, Jump$\}=14\text{'}$b$11\_0010\_1000\_0010//$lui $7\text{'}$b$001\_0111$ :$\{$RegWrite$,$ ImmSrc, ALUSrcA, ALUSrcB, MemWrite, ResultSrc, Branch, ALUop, Jump$\}=14\text{'}$b $//$auipc default : $\{$RegWrite$,$ ImmSrc, ALUSrc, MemWrite, ResultSrc, Branch, ALUop, Jump$\}=11\text{'}$hx; endcase end endmodule $.$