Question: module TB _ SM ( ) ; / / Testbench is given reg X , clk , rst; reg [ 1 : 0 ] Q;

module TB_SM(); // Testbench is given
reg X,clk,rst;
reg [1:0] Q;
SM UUT(X,clk,rst,Q);
always
begin
#10 clk = ~clk;
end
initial
begin
X =0;
rst =1;
clk =0;
#20
rst =0;
#20
if(Q ==0)
begin $display("test 1 passed");end
else
begin $display("test 1 failed");end
X =1;
#20
if(Q ==3)
begin $display("test 2 passed");end
else
begin $display("test 2 failed");end
X =0;
#20
if(Q ==01)
begin $display("test 3 passed");end
else
begin $display("test 3 failed");end
X =1;
#20
if(Q ==3)
begin $display("test 4 passed");end
else
begin $display("test 4 failed");end
X =1;
#20
if(Q ==3)
begin $display("test 5 passed");end
else
begin $display("test 5 failed");end
X =1;
#20
if(Q ==3)
begin $display("test 6 passed");end
else
begin $display("test 6 failed");end
X =0;
#20
if(Q ==1)
begin $display("test 7 passed");end
else
begin $display("test 7 failed");end
X =0;
#20
if(Q ==0)
begin $display("test 8 passed");end
else
begin $display("test 8 failed");end
X =0;
#20
$stop;
end
initial begin $dumpfile("dump.vcd");
$dumpvars; end
endmodule module SM(input reg X, clk, rst, output reg [1:0] Q);
reg [1:0] PS, NS;
// Implement code using the given testbench all tests should pass
endmodule
module TB_SM(); // Testbench is given reg X,clk,rst; reg [1:0] Q;

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