More on Dynamic RAM Chips

$$Consider $32$M $8$ chip with $16$K $16$K array

$16,384$ cells per row organized as $2048$ bytes

$14$ bits to select row, $11$ bits for byte in row

$$Use multiplexing of row$/$column on same pins

$$Row$/$column address latches capture bits

$$Row$/$column address strobe signals for timing

$($asserted low with row$/$column address bits$)$

$$Asynchronous DRAMs: delay$-$based access,

external controller refreshes rows periodically