mplement a simple and small

RISC CPU

$$ Only $11$ instructions to

implement

$$ Use $4$ bits for Opcode

$($Operational Code$)$

$$ Only $4$ registers

$2$ bits needed for each register

reference

$$ Use $4$ bits for beq$/$bne offset

$$ Go ahead at most $7$ instructions,

go back at most $8$ instructions

$$ Use $4$ bits for data and

constants

$0$ to $15,$ or $-8$ to $7$

$$ Constants are generally small

$$ Use $8$ bits for program

address

$$ Overall instruction is $12$ bits

wide

$$ We can later increase

number of registers or data

width size without affecting

the system architecture in logism