My ALU isn't working right and the opcode and enable should be grab by the FSM that i have already made can you fix it and make a testbench so it works?

module alu $($

input $[7$:$0]$ a$,//$ Operand A

input $[7$:$0]$ b$,//$ Operand B

input $[2$:$0]$ opcode, $//$ Operation opcode from FSM

input enable, $//$ Enable signal for ALU operation

output reg $[7$:$0]$ result, $//$ ALU result

output reg div$\_$by$\_$zero $//$ Flag to indicate division by zero

$)$;

$//$ ALU Operations based on opcode

always @$(*)$ begin

if $($enable$)$ begin

div$\_$by$\_$zero $=0$; $//$ Default to no division by zero error

case $($opcode$)$

$3\text{'}$b$000$: result $=$ a $+$ b; $//$ Addition

$3\text{'}$b$001$: result $=$ a $-$ b; $//$ Subtraction

$3\text{'}$b$010$: result $=$ a $*$ b; $//$ Multiplication

$3\text{'}$b$011$: begin

if $($b $==0)$ begin

result $=8\text{'}$b$0$; $//$ Division by zero case

div$\_$by$\_$zero $=1$; $//$ Set division by zero flag

end else begin

result $=$ a $/$ b; $//$ Division

div$\_$by$\_$zero $=0$; $//$ No error

end

end

$3\text{'}$b$100$: result $=$ a & b; $//$ AND

$3\text{'}$b$101$: result $=$ a $|$ b; $//$ OR

$3\text{'}$b$110$: result $=$ a $<<1$; $//$ Shift Left

$3\text{'}$b$111$: result $=$ a $>>1$; $//$ Shift Right

default: result $=8\text{'}$b$0$; $//$ Default to $0($error case$)$

endcase

end else begin

result $=8\text{'}$b$0$; $//$ If ALU is not enabled, output $0$

div$\_$by$\_$zero $=0$; $//$ No division by zero error if ALU is disabled

end

end

endmodule