Name:

Grade:

$10$

For a Flip$-$Flop Design with clock speed $4$ GHz$,1)$ sketch the timing diagram with following data and $2)$ find out maximum time could be used for logic design. Assume clock skew$($uncertainty$)$ is $0$ ps$.$

$\backslash$table$[[,$Set$-$up time,CLK$->$Q Delay,Contamination Delay,Hold Time$],[$Flip$-$Flop,$25$ ps$,15$ ps$,5$ ps$,20$ ps$]]$

If the clock uncertainty is $20$ ps $,$ repeat problem #$1.$