Question: Need this unsigned 4 x 4 multiplier to do signed multiplication. module Multiplier ( input Clock, Reset, / / declare inputs input [ 3 :

Need this unsigned 4x4 multiplier to do signed multiplication.
module Multiplier (
input Clock, Reset, //declare inputs
input [3:0] Multiplicand,
input [3:0] Multiplier,
output [7:0] Product, //declare outputs
output Halt);
reg [3:0] RegQ, RegM; // Q and M registers
reg [4:0] RegA; // A register
reg [1:0] Count; //2-bit iteration counter
wire C0, Start, Add, Shift;
assign Product ={RegA[3:0],RegQ}; //product = A:Q
//2-bit counter for #iterations
always @(posedge Clock)
if (Start ==1) Count <=2'b00; // clear in Start state
else if (Shift ==1) Count <= Count +1; // increment in Shift state
assign C0= Count[1] & Count[0]; // detect count =3
// Multiplicand register (load only)
always @(posedge Clock)
if (Start ==1) RegM <= Multiplicand; // load in Start state
// Multiplier register (load, shift)
always @(posedge Clock)
if (Start ==1) RegQ <= Multiplier; // load in Start state
else if (Shift ==1) RegQ <={RegA[0],RegQ[3:1]}; // shift in Shift state
// Accumulator register (clear, load, shift)
always @(posedge Clock)
if (Start ==1) RegA <=5'b00000; // clear in Start state
else if (Add ==1) RegA <= RegA + RegM; // load in Add state
else if (Shift ==1) RegA <= RegA >>1; // shift in Shift state
// Instantiate controller module
MultControl Ctrl (Clock, Reset, RegQ[0], C0, Start, Add, Shift, Halt);
endmodule
module MultControl (
input Clock, Reset, Q0, C0,//declare inputs
output Start, Add, Shift, Halt); //declare outputs
reg [4:0] state; //five states (one hot one flip-flop per state)
//one-hot state assignments for five states
parameter StartS=5'b00001, TestS=5'b00010, AddS=5'b00100, ShiftS=5'b01000, HaltS=5'b10000;
reg [1:0] Counter; //2-bit counter for # of algorithm iterations
// State transitions on positive edge of Clock or Resets
always @(posedge Clock, posedge Reset)
if (Reset==1) state <= StartS; //enter StartS state on Reset
else //change state on Clock
case (state)
StartS: state <= TestS; // StartS to TestS
TestS: if (Q0) state <= AddS; // TestS to AddS if Q0=1
else state <= ShiftS; // TestS to ShiftS if Q0=0
AddS: state <= ShiftS; // AddS to ShiftS
ShiftS: if (C0) state <= HaltS; // ShiftS to HaltS if C0=1
else state <= TestS; // ShiftS to TestS if C0=0
HaltS: state <= HaltS; // stay in HaltS
endcase
// Moore model - activate one output per state
assign Start = state[0]; // Start=1 in state StartS, else 0
assign Add = state[2]; // Add=1 in state AddS, else 0
assign Shift = state[3]; // Shift=1 in state ShiftS, else 0
assign Halt = state[4]; // Halt=1 in state HaltS, else 0
endmodule

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