Need within 15 mins emegency

1. What is SIM instruction? Explain briefly. 4 2. Consider a pipelined processor with the following four stages 6 IF: Instruction fetch ID: Instruction Decode and Operand Fetch EX: Execute WB: Write Back The IF ID and WB stages take one clock cycle each to complete the operation. The number of clock for the executive stage depends on the instruction. The ADD and SUB instructions need 1 clock cycle and the MUL instruction needs 3 clock cycle in the EX stage. Operand forwarding is used in the pipelining processor. What is the number of clock cycles are taken to complete the following sequence of instructions? ADD R2,R1,RO MUL R4,R3,R2 SUB R6,R5,R4