Optimizing Power @ Design Time (Architecture, Algorithms, and Systems)

Optimizing Power @ Design Time (Architecture, Algorithms, and Systems)

1)The power reduction can be in the order of 10X or more at system level, while at the logic level and below it is 50-60%. Explain why?

2)With an example, explain how concurrency can be exploited to reduce dynamic power consumption.

3)With an example, explain how pipelining can be exploited to reduce dynamic power consumption.

4)Explain with an example, how signal statistics can be leveraged to minimize power consumption.