Part I $$ SR Latch

Background

The simplest sequential circuit element is the SR latch. It presents two asynchronous inputs $($SET

$$that makes the device store a logic $1$ and RESET $$ an input that makes the device store a logic

$0)$ and two complementary outputs,

Q

and

Q

that are always in opposite logic states $($Figure

$5\mathrm{.}5\mathrm{.}1)$

The SR latch presents two stable states:

$$ SET or ON when

Q $=1$

and

Q $=0$