Performance and MIPS ISA

Consider this C/C++ code fragment:

int i, sum=0, x[10];

for (i=0; i<10; i++)

sum = sum + x[i];

The code fragment is translated to MIPS assembly language. I is allocated to $16. $18 is a pointer for referencing the array x[]; $18 has already been initialized to contain &x[0]. The variable sum is also allocated in memory; $20 contains &sum.

The MIPS code:

Or $16,$0,$0 # I=0

loop:Lw $19,($18) # load x[I]

Lw $21,($20) # load sum

Add $21,$21,$19 # sum = sum + x[I]

Sw $21,($20) # store sum

Addi $16,$16,1 # I++

Addi $18,$18,4 # ptr++

Slti $17,$16,10

Bne $17,$0,loop # if (I<10) goto loop

a) What is the instruction count for this code fragment? Make a table of the instruction counts of each type of instruction.

b) Suppose we run the above code fragment on a CPU called the CPU_base. We are given these CPI numbers for the main instruction types:

Instruction type CPI

Load/stores 3

Int ALU 1

Branches 2

(Hence, each load/store takes 3 cycles, each int ALU takes 1 cycle etc)

Calculate the number of cycles it takes for this code fragment to execute on CPU_base.