Pipeline hazards and reschedule the code to improve performance time:

Consider the following code segment in C:

A = B +E;

C = B + F;

The generated MIPS code for above segment is below, assuming all variables are in memory and are addressable as offsets from $t0:

lw $t1, 0($t0) # mem($t0) => $t1

lw $t2, 4($t0) # mem(4+$t0) => $t2

add $t3, $t1, $t2 # $t1 + $t2 => $t3

sw $t3, 12($t0) # $t3 => mem(12+$t0)

lw $t4, 8($t0) # mem(8+$t0) => $t4

add $t5, $t1, $t4 # $t1 + $t4 => $t5

sw $t5, 16($t0) # $t5 => mem(16 + $t0)

On a pipelined processor with forwarding,

(a) Find the data hazards (indicate the instructions with data hazards) of above code.

(b) Reorder the instructions to avoid any pipeline stalls.

(c) Draw the pipelines and compare. How many fewer cycles will the reordered sequence take than the original version?