Question: please answer in VHDL 3) Write an entity declaration and behavioral architecture for a 2 to 1 multiplexer, with input ports a, b, and sel

please answer in VHDL
3) Write an entity declaration and behavioral architecture for a 2 to 1 multiplexer, with input ports a, b, and sel (select), and an output port y. The input and output ports are all single bit. Write a VHDL test bench to test your multiplexer model. Simulate the model and the test bench to demonstrate correct operation
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