Question: Please clearly explain/answer the problem, and show any calculation if necessary. Assuming stall-on-branch and no delay slots, what speedup is achieved on this code if

Please clearly explain/answer the problem, and show any calculation if necessary.

Assuming stall-on-branch and no delay slots, what speedup is achieved on this code if branch outcomes are determined in the ID stage, relative to the execution where branch outcomes are determined in the EX stage? The remaining problems in this exercise assume that individual pipeline stages have the following latencies: IF: 200ps ID: 120ps EX: 150ps MEM: 190ps WB: l00ps IF: 150ps ID: 200ps EX: 200ps MEM: 200ps WB: l00ps

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