please explain how to do the following question

Consider the following circuit, consisting of two D flip-flops (1-bit registers), a 1-bit input A, and a 1-bit output Z. 1. CLK 0 CLK Den Complete the timing diagram for this circuit. You must have a value for Q1, Q2, and Z for cycles 1-7. Do not use Logisim for this exercise. As shown, the input A is given, and the flip-flops are both initially holding 0 CLK Q1 Q2