please fully explaination.

Consider a cache hierarchy with a 4KB direct-mapped L1 cache and 1MB 4-way associative L2 cache. Suppose the L1 has a Toit of 2 cycles, the L2 has a tour of 10 cycles, and the L2 has a Liss of 200 cycles. Assume the miss time does not include the time to figure out if we have a hit or not. Answer the following questions: 1. What would be the average memory access time if the L1 has a hit rate of 95% and the L2 has a hit rate of 70%? Assume accesses are only sent to the L2 if they miss in the L1. 2. The architect team decides to add an LO cache of 1KB to the cache hierarchy. The LO would have a 1 cycle access time and memory requests would only be passed on to the L1 if the LO missed. What hit-rate would be required to achieve a 10% improvement in average memory access time? (Use the hit-rate numbers from the previous question as needed.) A Processor team is trying to improve memory system performance in its next-generation processor design. Their current design has a 64KB 2-way L1 and a 512KB 4-way L2. The L1 has a hit time of 2 cycles, the L2 access latency is 12 cycles, and the main memory access latency is 250 cycles. For applications that are used to evaluate their design, they achieve a 5% L1 miss rate and a 40% (local) L2 miss rate. 1. What is the effective access time of their current design? 2. The team is considering increasing the L2 to a 2MB 16-way design. The larger L2 has a 16 cycle access latency. What must the (local) L2 miss rate of the new design be to achieve a 20% reduction in overall average memory access time