please help as soon as possible. Include verilog code , test bench and simulation please

The BCD counter circuit has one input clk, and four-bit output signal dout. The dout signal counts from 0 to 9 and then repeats. clk dout[3:0) BCD Figure 4. BCD counter diagram Implement this design in Verilog and write testbench to run simulations. Check the simulation waveform to verify that the BCD counter can output a value from 0 to 9 on each rising edge of the clk signal, and then repeat the execution