Please help me out with this question. it has two parts, work shown in detail is required so i can understand it

PART A

PART B

4.8 In this exercise, we examine how pipelining affects the clock cycle time of the processor. Problems in this exercise assume that individual stages of the data path have the following latencies: IF: 250ps ID:350ps EX:150ps MEM:300ps WB: 200psAlso assume that instructions executed by the processor are broken down as follows: alu:45% beq:20% lw:20% sw:15% 4.8.1What is the clock cycle time in a pipelined processor? ps What is the clock cycle time in a non-pipelined processor? ps 4.8.2 What is the total latency of an "lw" instruction in a pipelined processor What is the total latency of an "lw" instruction in a non-pipelined processor. ps ps 4.8.3 If we can split one stage of the pipelined datapath into two new stages, each with half the latency of the original stage which stage would you split? (Choose the answer from IF ID EX MEM WB) What is the new clock cycle time of the processor? ps 4.8.4 Assuming there are no stalls or hazards, what is the utilization of the data memory? (Hints: consider only instructions lw and sw) 4.8.5 Assuming there are no stalls or hazards, what is the utilization of the write-register port of the "Registers" unit? (Hint: Alutlw)