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Two implementations of an 8-tap FIR filter are shown in Figure 4. Assume the critical path of a multiplier to be twice that of an adder, that is, Tru: = 27a. Therefore, the charging capacitance of a multiplier is twice that of an adder. Further assume that the total capacitance of a multiplier is 10 times that of an adder, that is, Cru = 10Cad. The critical path of the direct form structure in Fig. 4{a) is Tru +7 Tada = 9 Togs. The structure in Fig. 4(b) can be operated with a lower supply voltage to meet the clock period or sampling period constraint of 9Tas. Thus, the structure in Fig. 4(b) can be used to reduce power consumption. Assume the structure in Fig. 4(a) is operated with a supply voltage of Von = 1 V and the technology threshold voltage to be V7 = 0.2 V. The supply must be greater than 0.3 V to achieve the acceptable noise margin. D | PEP PETE: @) ) ) ) 0 fal rin) yin) am DP D P (