Please help me write a controller module in verilog that follows the behavior of the table and utilizes the module defintion of the skeleton code given below. Thank you!

$`$ timescale $1$ ns $/1$ ps

$//$ Module definition

module Controller $($

Opcode $,$

ALUSrc $,$ MemtoReg $,$ RegWrite $,$ MemRead $,$ MemWrite $,$

ALUOp

$)$;

$//$ Define the input and output signals

$//$ Define the Controller modules behavior

endmodule $//$ Controller

With the information in Table $2,$ we can design the Controller.

The MemtoReg signal is $\text{'}0\text{'}$ for all instructions except for the "Load" instruction

The MemWrite signal is $\text{'}0\text{'}$ for all instructions except for the "Store" instruction

The MemRead is also $\text{'}0\text{'}$ for all instructions except for the "Load" instruction

The ALUSrc is $\text{'}1\text{'}$ when the opcode is $"0010011"$ or $"0000011"$ or $"0100011".$ For these instructions, source B operand comes from the imm$\_$Gen. For other instructions with opcode $"0110011",$ ALUSrc is $\text{'}0\text{'}$ Because both of the Source operands of the ALU come from the register file.

RegWrite is $\text{'}1\text{'}$ except for the "Store" instructions. This is because for all of these instructions we want to write back the result to the register file.

The ALUOp$(1$ downto $0)$ is $"10"$ when the opcode is $"0110011"$ and $"00"$ when the opcode is $"0010011".$ It is also $"01"$ for the "Load" and "Store" instructions with opcodes $"0000011"$ and $"0100011"$ respectively.

Table $2$ : Control Signals.

$\backslash$table$[[,$Opcode,$],[,,0110011,0010011,0000011,0100011],[,,\backslash$table$[[$AND$,$ OR$,$ ADD,$],[$SUB$,$ SLT$,$ NOR$]],\backslash$table$[[$ANDI$,$ ORI, ADDI,$],[$SLTI$,$ NORI$]],$LW$,$SW$],[\backslash$table$[[-]],$MemtoReg,$0,0,1,0],[$MemWrite$,0,0,0,1],[$MemRead$,0,0,1,0],[$ALUSrc$,0,1,1,1],[$Regwrite$,1,1,1,0],[$ALUOp$,10,00,01,01]]$