Please help with computer class:

Suppose a CPU with a write$-$through, write allocate cache achieves a CPI of $2.$ The

Data Reads per $1000$ instructions is $200,$ the Instruction Cache Miss Rate is $0\mathrm{.}3\%,$

the Data Cache Miss Rate is $2\%$ and the Block S ize is $64$ bytes. What is the read

bandwidth $($measured by bytes per cycle$)$ between RAM and the cache? $($Assume

each miss generates a request for one block.$)$

a$)0\mathrm{.}128$ bytes per cycle

b$)0\mathrm{.}16$ bytes per cycle

c$)0\mathrm{.}064$ bytes per cycle

d$)0\mathrm{.}08$ bytes per cycle