a) Suppose a CPU with a write-through write-allocate cache achieves a CPI of 2. What are the read and write bandwidths (measured by bytes per cycle) between RAM and the cache? (Assume each miss generates a request for one block.)

b) For a write-back, write allocate cache, assuming 30% of replaced data cache blocks are dirty, what are the read and write bandwidths needed for a CPI of 2?

Data Reads per 1000 instructions	Data Writes per 1000 instructions	Instruction Cahce Miss Rate	Data Cache Miss Rate	Block size (Bytes)
250	100	0.30%	2%	64