please provide all files. I am using a DE10-lite board for this class. this has to be in Vhdl language.

4. Develop logic files for a BCD to Seven-Segment Display and HEX to Seven-Segment Display a. The input for one logic file will be a BCD value on [SW(3)-SW(0)] evaluated by a when/else statement, and displayed on a seven segment display [HEX0]. The other logic file will be a HEX value on [SW(9)-SW(6)] evaluated by a with/select, and displayed on a seven segment display [HEX5]. Use a component declaration and port map implementation to accomplish this. Demo your board implementation 4. Develop logic files for a BCD to Seven-Segment Display and HEX to Seven-Segment Display a. The input for one logic file will be a BCD value on [SW(3)-SW(0)] evaluated by a when/else statement, and displayed on a seven segment display [HEX0]. The other logic file will be a HEX value on [SW(9)-SW(6)] evaluated by a with/select, and displayed on a seven segment display [HEX5]. Use a component declaration and port map implementation to accomplish this. Demo your board implementation