Please provide the answer as well as how to solve this problem:

Consider a processor with $28$ bit physical addresses. Assume memory is byte addressable and

a$)$ There is a $12$ K bytes L$1$ instruction cache, which is three$-$way set associative, with $64$ bytes per block

b$)$ There is a $32$ K bytes Ll data cache, which is four$-$way set associative, with $64$ bytes per block

c$)$ Specify the number of offset, index $($set number$),$ and tag bits for each of the structures in the following table