Please show all work.

Consider an unpipelined or single-stage processor design like the one discussed class (Refer to slides). At the start of a cycle, a new instruction enters the processor and is processed completely within a single cycle. It takes 1,000 ps to navigate all the circuits in a cycle. Therefore, for this design to work, the cycle time has to be at least 1,000 pico seconds. 1. What is the clock speed of this processor? 2. What is the CPI of this processor, assuming that every load/store instruction finds its instruction/data in the instruction or data cache? (The instruction/data cache ensures that there are no latencies involved in fetching from additional on-board memory). 3. What is the throughput of this processor (in billion instructions per second)