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Assume that logic blocks needed to implement a processor's datapath have the following latencies. Ignore the Program Counter adder, i.e., PC+4. Start counting the latencies from instruction memory. a. [2 points] How much time a load instruction will take for nonpipelined processer with above latencies? Iw $st, offset(\$s1) b. [2 points] How much time a store instruction will take for nonpipelined processer with above latencies? sw \$t2, offset(\$s1) c. [2 points] How much time a sub instruction will take for nonpipelined processer with above latencies? sub \$t1, \$s1, \$s2 d. [2 points] How much time a branch instruction will take for nonpipelined processer with above latencies? beq$s1,$s2,16 e. [2 points] How much time a Jump instruction will take for nonpipelined processer with above latencies? Jump target Scan your work for Question 2