Please simulate in QUARTUS II only. Show the schematic capture and simulation for both.

part 1.

library IEEE; use IEEE.STD_LOGIC_1164.ALL;

entity nandgates is Port ( w : in STD_LOGIC; x : in STD_LOGIC; y : in STD_LOGIC; z : in STD_LOGIC; f1 : out STD_LOGIC; f2 : out STD_LOGIC); end nandgates;

architecture Behavioral of nandgates is component nand_1 is port(A,B: in std_logic; C: out std_logic); end component nand_1; signal p,q,s1,s2 : std_logic; begin p<= not w; q<= not x;

x1: nand_1 port map(p,q,s1); x2: nand_1 port map(q,z,s2); X3: nand_1 port map(s1,s2,f1);

end Behavioral;

part 2:

entity part2 is Port ( w,x,y,z: in STD_LOGIC; f1 : out STD_LOGIC); end part2; architecture Behavioral of part2 is begin process (w,x,y,z) variable v_CONCATENATE : std_logic_vector(3 downto 0); begin v_CONCATENATE := w&x&y&z; case v_CONCATENATE is when "0000" => f1<= '1'; when "0001" => f1<= '0'; when "0010" => f1 <= '1'; when "0011" => f1 <= '1'; end case; end process; end Behavioral;