Please solve the following problems assuming that the op$-$amps are ideal unless otherwise specified.

Fig. $1$ shows a logic circuit, which consists of two cross$-$coupled NAND gates of the same size.

Fig. $1$: A logic circuit

$($a$)$ Fill in the state transition table.

$($b$)$ We want to design the logic circuits so that the propagation delay of the output $Q(n+1)$ is less than $12\mathrm{.}5{10}^{-12}sec.$ when the input $\{ABQ(n)\}$ changes from $\{111\}$ to $\{101\}.$ Determine the proper $\frac{W}{L}$ values for $M_3,M_4,$ and $M_6.$ Assume the following parameters:

${}_n{C}_{ox}=1m\frac{A}{V^2}$

${}_p{C}_{ox}=500\frac{A}{V^2}$

$t_{PHL}\frac{1\mathrm{.}5C}{{}_n{C}_{ox}(\frac{W}{L}{)}_n{V}_{DD}},t_{PLH}\frac{1\mathrm{.}5C}{{}_p{C}_{ox}(\frac{W}{L}{)}_p{V}_{DD}}$

Total capacitance at the Q node: $C=10{10}^{-15}F.$