please solve this problem

Question $2)$ Below is a list of $32-$bit memory address references, given as byte addresses.

$1,182,212,231,162,1,184,161,25,2$

Consider the following two cache designs:

C$1$: $64$B direct$-$mapped cache with block size of $16B$

C$2$: $64$B fully associative cache with FIFO replacement policy and block size of $16$B

a$)$ Fill in the following table appropriately and calculate the miss rates of the caches.

$\backslash$table$[[$Address$,\backslash$table$[[$Binary$],[$address$]],\backslash$table$[[$C$1],[$Tag$]],\backslash$table$[[$C$1],[$Index$]],\backslash$table$[[$Hit$/],[$Miss$]],\backslash$table$[[$C$2],[$Tag$]],\backslash$table$[[$Hit$/],[$Miss$]]],[1,00000001,,,,,],[182,10110110,,,,,],[212,11010100,,,,,],[231,11100111,,,,,],[162,10100010,,,,,],[1,00000001,,,,,],[184,10111000,,,,,],[161,10100001,,,,,],[25,00011001,,,,,],[2,00000010,,,,,]]$

C$1$ miss rate:

C$2$ miss rate:

b$)$ Assuming that the miss stall time is $25$ cycles, and $C1$ has an access time of $2$ cycles and C$2$ has an access time of $4$ cycles, calculate the average memory access times of the caches.