This exercise examines the impact of different cache designs, specifically comparing associative caches to the direct-mapped caches from Section 5.4. Below is a list of 32-bit memory address references, given as byte addresses 3, 180, 43, 2, 191, 88, 190, 14, 181, 44, 186, 253 Using the sequence of references from above, show the final cache contents for a three-way set associative cache with two-word blocks and a total size of 24 words. Use LRU replacement. For each reference identify the index bits, the block offset bits, and if it is a hit or a miss. Using the references from above, show the final cache contents for a fully associative cache with one-word blocks and a total size of 8 words Use LRU replacement. For each reference identify the index bits, the block offset bits, and if it is a hit or a miss