Please Write it in VHDL and complete the following code

Create an entity called framebuffer" where you infer a dual port memory consisting of 4096 16-bit words (8 KiB). It should have the following black box interface and behavior. /Notice how we have two different enables going into this device. The CPU side and the video display side are on two different clock domains, operating independently of 4 memory. Otherwise we would have to navigate access with a controller and some FIFOs/ entity framebuffer is port clkl, enl, en2, ld in std logic; addrl, addr2 in std logic vector (11 downto 0) wr_enl: in stdlogic; in std_logic vector (15 downto doutl, dout2 out std logic vector (15 downto 0) end framebuffer; Create an entity called framebuffer" where you infer a dual port memory consisting of 4096 16-bit words (8 KiB). It should have the following black box interface and behavior. /Notice how we have two different enables going into this device. The CPU side and the video display side are on two different clock domains, operating independently of 4 memory. Otherwise we would have to navigate access with a controller and some FIFOs/ entity framebuffer is port clkl, enl, en2, ld in std logic; addrl, addr2 in std logic vector (11 downto 0) wr_enl: in stdlogic; in std_logic vector (15 downto doutl, dout2 out std logic vector (15 downto 0) end framebuffer