Prelab: Generate the minimum SOP logic functions for all segments of the 7-segment display described in part 1 of this lab. Write a description of this circuit in WINCUPL. Find and print (or save a digital copy of) the relevant portions of the datasheet for the chips we will be programming (ATMEL ATF16V8B). You will also need a detailed plan for testing the delay of each output of your circuit (note that since we can't predict what the worst case is for the programmable chips, we must measure delay for each output from at least one input to estimate the worst case). Your plan should be sufficiently specific that if you switched plans with another lab group, each of you could still measure all output delays. Pre-lab to be checked: Your truth table and K-maps for all outputs, your detailed test plan, WINCUPL code, and the datasheet for the programmable chip (the datasheet can be a digital copy, but you must have it viewable on a notebook or lab desktop). This should all be completed before you arrive in lab