Prob $2.(40$ points, $10$ points each$)$ Consider the setup of a $16-$bit timer that has a $16-$bit prescaler. Assume the

input clock to the timer has a clock with $f_{C{L}_{P}SC}=65\mathrm{.}54MHz.$ Answer the following questions:

What is the lowest rate of the interrupt pulse of the timer if the timer is set up to be edge$-$aligned

up$-$counting without the prescaler?

How can we choose the values of the PSC and the ARR so that we can have $f_{CL}CNT=10kHz$ and the

output interrupt rate of the timer being $10Hz$ using the edge$-$aligned up$-$counting mode?

Suppose we inadvertently set up the mode to centered$-$aligned with the same values of the PSC and the

ARR as before. What is the interrupt rate of the timer when we only use overflow?

Continue to Part $3.$ What is the resolution of the interrupt generation in terms of time?