Question: Problem 1 [40 pts] Design a Verilog code for 5x5 array multiplier. Use structural Verilog description with full adders and half adders. Submit your codes

Problem 1 [40 pts] Design a Verilog code for 5x5 array multiplier. Use structural Verilog description with full adders and half adders. Submit your codes and test results with waveform. Use your freedom as Verilog designer in deciding input/output variables, number of bits, control signals, etc.

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