Problem $2(20$ pts$,5/5/5/5)2.$ The instruction execution of a computer can be divided into five

stages as follows: IF$,$ ID$,$ EX$,$ MEM and WB$.$ The measured times for the stages are: $1$ns$,1\mathrm{.}5$ns$,1$ns$,$

$2ns,$ and $1\mathrm{.}5ns,$ respectively.

$($a$)$ What is the clock cycle time if the instruction execution is implemented as a single$-$cycle implemen$-$

tation?

$($b$)$ What is the clock cycle time if the instruction execution is implemented as a multiple$-$cycle imple$-$

mentation?

$($c$)$ What is the clock cycle time if the instruction execution is implemented as a pipelined implementa$-$

tion?

$($d$)$ What is the speedup of the pipelined implementation over the single$-$cycle implementation?