Problem 2: (20 points) Consider the following VHDL code: library ieee; use ieee.std_logic 1164.all; use ieee.std_logic_unsigned.all; entity prob2 is port( clk: in std_logic; clear, go, load: in std_logic; hex0: out std_logic_vector (6 downto 0) end prob2 architecture arch of prob2 is signal d_reg, d_next std_logic_vector (3 downto O signal t_reg, t_next: std_ logic_vector (26 downto 0) begin process (clk) begin if (clk' event and clk-'1') then d_reg c d_next; t reg