Problem 2

(60 Points) Design a MIPS processor supporting only the R-type and the jset rs, rt, rd instructions. The jset rs, rt, rd instruction does the following: If rs is not equal to rt, the next PC is the memory content at rs-rt and rd is set to be rs-rt; otherwise, the next PC is PC+4 and register $ra is also set to be PC+4. Recall that $ra is the special register, $31, used in the jal instruction. For example, If rs and rt are 20 and 8 respectively, rs != rt so rd will be 12 and PC will be the memory content at 12. If rs and rt are 20 and 20 respectively, rs == rt so rd will not change and PC and $ra will be set to PC+4 Assume that the opcode of R-type is 000000 and the opcode of jset is 100000.

b) (20 points) Consider the control signals for the 2-1 MUX. Fill in the following table (you should not need more than 4 2-1 MUXes). In the case of a dont care, write down a 0. Then determine the logic functions for each MUX. Specific bits in the instruction can be denoted as, for example, ins[31]. The ALU zero output can be referred to as z. Make sure to label your MUXes correctly.

Problem 2 (60 Points) Design a MIPS processor supporting only the R-type and the jset rs, rt, rd instructions. The jset rs, rt, rd instruction does the following: If rs is not equal to rt, the next PC is the memory content at rs-rt and rd is set to be rs-rt; otherwise, the next PC is PC+4 and register Sra is also set to be PC+4 Recall that Sra is the special register, $31, used in the jal instruction. or example, If rs and rt are 20 and 8 respectively, rs-rt so rd will be 12 and PC If rs and rt are 20 and 20 respectively, rs-= rt so rd will not change Assume that the opcode of R-type is 000000 and the opcode of jset is will be the memory content at 12 and PC and Sra will be set to PC+4 100000 b) (20 points) Consider the control signals for the 2-1 MUX. Fill in the following table (you should not need more than 4 2-1 MUXes). In the case of a "don't care", write down a 0. Then determine the logic functions for each MUX. Specific bits in the instruction can be denoted as, for example, ins/31/. The ALU zero output can be referred to as "z". Make sure to label your MUXes correctly R-type | Jset (rs != rt) | jset (rs == rt) MUXCtrll MUXCtrl2 MUXCtrl3 MUXCtrl4 Problem 2 (60 Points) Design a MIPS processor supporting only the R-type and the jset rs, rt, rd instructions. The jset rs, rt, rd instruction does the following: If rs is not equal to rt, the next PC is the memory content at rs-rt and rd is set to be rs-rt; otherwise, the next PC is PC+4 and register Sra is also set to be PC+4 Recall that Sra is the special register, $31, used in the jal instruction. or example, If rs and rt are 20 and 8 respectively, rs-rt so rd will be 12 and PC If rs and rt are 20 and 20 respectively, rs-= rt so rd will not change Assume that the opcode of R-type is 000000 and the opcode of jset is will be the memory content at 12 and PC and Sra will be set to PC+4 100000 b) (20 points) Consider the control signals for the 2-1 MUX. Fill in the following table (you should not need more than 4 2-1 MUXes). In the case of a "don't care", write down a 0. Then determine the logic functions for each MUX. Specific bits in the instruction can be denoted as, for example, ins/31/. The ALU zero output can be referred to as "z". Make sure to label your MUXes correctly R-type | Jset (rs != rt) | jset (rs == rt) MUXCtrll MUXCtrl2 MUXCtrl3 MUXCtrl4