PROBLEM $2$

Assume that the following code segment is run on a MIPS like processor with hazard detection and forwarding, in order, $5$ stages pipeline $($F $($instruction fetch$),$ D $($instruction decode$),$ E $($execute$),$ M $($memory access, W $($write$-$back$)),$ static not taken branch prediction $($branches are always predicted as not taken$),$ etc.. Below is the code segment that is running on the processor.

# code segment

beq $R$1,$ $R$0,$ L$2$

L$1$: sw $R$2,100($$R$1)$ # $R$2->$ M$[$$R$1+100]$

shl $R$2,$ $R$2,1$

beq $R$1,$ $R$0,$ L$3$

L$2$: lw $R$2,100($$R$1)$ # M$[$$R$1+100]->$ $R$2$

addi $R$2,$ $R$2,100$

addi $R$3,$ $R$3,1$

beq $R$1,$ $R$0,$ L$1$

L$3$: END

Note: END is an assembly directive, not an instruction and should not be counted as an instruction.

a$)$ How many cycles does this program take? Assume all data and instructions are already in the cache, and that all register values are initially $0.$ The branches are always going to be evaluated as not taken and they require two stall clock cycles each.

b$)$ An optimizing compiler is used to re$-$order the code for faster execution. Given that the branches are always going to be $$not taken$,$ how would the new code look like? How many cycles would the code take?