Problem #2 Consider a 5-stage pipeline with (IF, ID, EX, MEM, WB), full data forwarding (including from MEM stage to ID stage), hazard detection unit, and branch instruction is executed in ID stage and 1 delay slot for branches. Assume that the first half of the clock cycle write-back stage writes to register file and the second half of the clock cycle the decode stage performs a read of source registers. Show a pipeline execution diagram for the following program, where all data forwards are marked with arrows and stalls are marked with **. You can insert NOPs in addition to stalls (if needed for the correct operation of the code). I1: lw $2, 100($3); I2: lw $2, 0($2); I3: sw $2, 100($4); I4: and $2, $2, $1; I5: beq $9, $1, Target; I6: and $9, $9, $1;