Problem $2$:

Consider a dynamically scheduled single$-$issue processor that uses Tomasulo$$s algorithm with the following

execution latencies:

$2$ cycles for LD $(+1$ cycle for address computation$)$

$2$ cycles for SD $(+1$ cycle for address computation$)$

$2$ cycles for integer add$/$sub

$3$ cycles for double precision add $($ADDD$)$

$6$ cycles for double precision multiply $($MULTD$)$

$10$ cycles for double precision divide $($DIVD$)$

Also assume that the number of reservation stations we have for load, store, integer add$/$sub$,$ double

precision add$/$sub$,$ and double precision multiply$/$divide are $1,1,2,1,$ and $3$ respectively. Finally assume that

if two instructions are ready to write their results back in the same clock cycle, the priority will be given to

the oldest instruction $($based on program order$).$

Consider the program segment below:

I$0$: LD F$2,0($Rx$)$

I$1$: DIVD F$8,$F$2,$F$0$

I$2$: MULTD F$2,$F$6,$F$2$

I$3$: LD F$4,0($Ry$)$

I$4$: ADDD F$4,$F$0,$F$4$

I$5$: ADDD F$10,$F$8,$F$2$

I$6$: ADDI Rx$,$Rx$,$#$8$

I$7$: ADDI Ry$,$Ry$,$#$8$

I$8$: SUB R$20,$R$4,$Rx

I$9$: SD F$4,0($Ry$)$

Show the status of each instruction, the reservation stations $($including load$/$store buffers$),$ and the registers

status at cycle $11.$ How many cycles does it take for the program segment below to finish execution? For each

instruction show when it issues, when it finishes execution, and when it writes its result.