Problem #$2$

The following is a typical assembly language instruction from the MIPS instruction set architecture.

ADD $s$3,$ $t$2,$ $s$1$

This instructs the CPU to add the contents of registers t$2$ and s$1$ together and to store the result in s $3.$

In order to execute this instruction in one instruction cycle, the CPU needs to simultaneously read from

two independently$-$specified registers $($meaning that they may or may not be the same register$),$ and

write to a third independently$-$specified register. This is usually referred to as a triple$-$ported register file.

Using the standard Hack parts, design a triple$-$ported register file containing eight $16-$bit registers. The

interface to this part is as follows:

$IN$: rae$[3],ra1[3],wa[3],wd[16],$ load;

OUT: rde$[16],rd1[16]$;