Problem 3 (20) A finite state machine has one input and one output. The output becomes 1 and remains 1 thereafter when at least two O's and two 1's have occurred as inputs, regardless of the order of appearance. A. (10)Draw a state transition diagram for the machine (implement as a moore machine). Hint: You can do this in nine states. B. (10) Write a Verilog module that implements the machine. Your module should have the following inputs/outputs. CLK For the clock RESET asserted high to reset the FSM to its initial state ONE asserted high to input a "1". Note that this signal may stay high for many cycles (eg, it's generated by a button press) before returning low. Each high period should count as a single "1" input, ie, to inputs two "1"s in series, the signal must return low inbetween the first and second "1". ZERO asserted high to input a "0". This signal has the same timing algorithm as ONE above. OUT asserted high when at least two "O's and two "1"s have occurred as inputs. Assume that all inputs have been externally synchronized with clk. Derivables: --A text file (pdf or word) for the options a. -- ascii text file of the verilog codes. -- zipped verilog project