Problem 3: A Mealy sequential network is implemented using the network shown below. Assume that if the input Xchanges, it changes at the same time as the falling edge of the clock Assume the following delays: XOR gate, 5 to 15 ns; flip-flop propagation delay, 5 to 15 ns, setup time, 10 ns; hold time, 5 ns. Initially assume that the "delay" is 0 ns. D D Delay gallery so Clock a) Determine the maximum clock rate for proper synchronous operation b) Assume a clock period of 100 ns. What is the maximum value that "delay" can have and still achieve proper synchronous operation? a) Complete the following timing diagram. Indicate the proper times to read the output (Z). Assume that "delay" is ons and that the propagation delay for the flip-flop and XOR gate has a nominal value of 10 ns. Clock X 2 Z