Problem $3.$ Pipelining

a$)$ The pipelined datapath has a register file that WRITES during the FIRST half of the clock cycle and READS during the SECOND half of the clock cycle. Instructions can be stalled only in the instruction$-$fetch and instruction$-$decode stages. There is a bypass $($forwarding$)$ from the output of the WB stage to the EX stage $($output of the MEM$/$WB register to the input of the logic in the EX stage$).$ Fill the pipeline timing diagram and indicate in which cycle the "add" instruction from the next iteration appears in the pipeline assuming branches are resolved in the MEM stage.